In a processor or processor core with hardware multithreading support (MTP=Multithreading Processor), several threads can be executed concurrently. In the following, the term thread is used as synonym for what is also called a routine, a set of instructions, a task or a process according to technical language. Due to cache misses, coprocessor use or synchronization mechanisms some of the threads may have to wait for a limited amount of time. In this time instructions from these threads can not be executed. Typically the remaining threads compete for the processing resources/execution pipelines such as arithmetic-logic-units or memory interfaces. Threads can be executed in parallel in different execution pipes and competition is for one or more of these execution pipes. This competition has to be resolved by selecting one or more threads whose instructions will be executed next.
If no control of the way instructions are issued exists in such processors, a single thread can be executed slower than it would be executed on a single thread processor system. Recently, MTP have been used for systems with real-time constraints as well, e.g. network and media processors. In these fields the execution time requirements of threads may vary depending on several issues. Therefore it is important to guarantee thread execution differentiation. To that end, a mechanism that controls the way instructions are issued from threads is of high value.
The current methodologies investigated and discussed in the literature mainly concentrate on improving the overall throughput of a multithreaded processor.
U.S. Pat. No. 6,105,127 discloses a multithreaded processor for executing multithreaded instructions stream. A control unit is provided for deciding which instruction should be issued to a functional unit designated by two or more instruction issues requests at the same time, in accordance with priority levels held by a holding unit.
U.S. Pat. No. 6,212,544 B1 discloses a method for controlling the switching between at least two threads. Priorities are incorporated by a thread state register comprising a thread priority field for one of three priority values—low, medium, high.
U.S. Pat. No. 6,477,562 B2 introduces instruction scheduling for multi-streaming processors. A priority controller generates priorities for instruction selection and access rights to certain resources.
In many systems, tasks of varying importance are assigned to the threads of a processor. In such a situation, the instruction selection process has to be controlled to guarantee that the most important tasks are executed first and thus, fast. At the same time, the effort of the control of instruction selection should be very low, because it impacts—and in particular reduces—the total amount of processing capacities for applications.
Thus, it is desired to provide a method and an apparatus for determining a priority value for a thread for execution on a multithreading processor system, that defines the priority value of a thread in a way that takes the true need of execution at the time into account.